In certain communication systems, multiple devices transmit data to a controller via a communication channel (e.g., a single-wire bus) that is logically divided into a number of successive time slots, with each time slot having a predetermined number of bits. Each device transmits data to the controller in one or more designated time slots according to a slot allocation scheme, which is fixed in some communication systems and variable in other communication systems. Often times, the devices transmit at fixed regular intervals, and therefore the communication channel is often logically divided into a number of frames with each frame containing a predetermined number of time slots, and each device transmits in its respective time slot(s) in each frame. Thus, for example, a first device may transmit in the first time slot of each frame, a second device may transmit in the second time slot of each frame, and so on. In some systems, devices may transmit in multiple time slots, for example, a first device may transmit in the first and second time slots of each frame, a second device may transmit in the third and fourth time slots of each frame, and so on. In some systems, different devices may transmit in different numbers of time slots, for example, a first device may transmit in the first time slot of each frame, a second device may transmit in the second and third time slots of each frame, a third device may transmit in the fourth time slot of each frame, and so on.
For convenience, N will be used herein to represent the number of time slots per frame, B will be used herein to represent the number of bits per time slot, and M will be used herein to represent the number of devices. A particular embodiment might have, for example, eight 32-bit slots per frame (i.e., N=8, B=32), although the present invention is not limited to any particular values of N and B. The actual data transmitted in each time slot may use all B bits or may use fewer than all B bits (e.g., a 24-bit sample of digital audio may be conveyed in a 32-bit time slot). In various systems, there may be a one-to-one relationship between SCK and bits (e.g., one cycle of SCK for each bit) or there may be other relationships between SCK and bits (e.g., two or more cycles of SCK for each bit).
FIG. 1 schematically shows an exemplary system having a number of devices 1041-104M that transmit data to controller 102 in a TDM fashion, as known in the art. In this exemplary configuration, the controller acts as a bus master and all of the slaves operate as slave devices. The controller 102 provides a clock signal (SCK) and a frame synchronization signal (WS) to all of the devices 104. The controller 102 also sends commands to the devices 104 (e.g., based on a unique address for each device 104) over one or more command lines, for example, to configure the time slot(s) for each device 104 to transmit data over the data line (SD). Based on the SCK and FS signals, and the configuration information provided by the controller 102, each device 104 transmits in one or more designated time slots on the SD line.
FIG. 2 schematically shows another exemplary system having a number of devices 2041-204M that transmit data to controller 202 in a TDM fashion, as known in the art. In this exemplary system (which is similar to configurations shown and described in United States Publication US 2008/0069151 entitled “Variable Time Division Multiplex Transmission System” and filed by Satoh et al., which is hereby incorporated herein by reference in its entirety), each of the devices 204 includes both master operating logic and slave operating logic, and the operational mode of each device 204 may be set, for example, using a hardware pin on the device. In this exemplary embodiment, the first device 2041 is set to operate as the bus master (e.g., via the M/S pin) and provides a clock signal to both the controller 202 and the other devices 204, which are set to operate as slave devices (e.g., via the respective M/S pin). The device 2041 also provides a frame synchronization signal to the controller 202 to mark the start of each frame and provides a delayed synchronization signal to the second device 2042 in the chain to mark the start of that device's time slot(s). Each slave device in the chain, beginning with the second device 2042, provides a delayed frame synchronization signal to the next successive device in the chain.
A similar system is shown and described in Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC (Texas Instruments, Revised April 2005), which is hereby incorporated herein by reference in its entirety. Specifically, FIG. 20 of this document shows a number of devices in a cascade connection, where the first device in the cascade is configured as a master device and both the DSP and the remaining devices in the cascade operate as slaves of the master device. Each slave device is configured to provide a delayed frame synchronization signal to the next successive slave device, and the devices are capable of automatically determining the number of devices in the cascade and automatically assigning addresses to the devices. One issue with such a configuration is that all of the devices carry both master and slave logic, with the master/slave operation of the device selected by the M/S pin. Among other things, the ability of each device to operate as a master or slave adds cost and complexity to each device.